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IPPS
2006
IEEE
16 years 1 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
ANCS
2006
ACM
16 years 1 months ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu
SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
16 years 24 days ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...
ACMMSP
2005
ACM
115views Hardware» more  ACMMSP 2005»
16 years 23 days ago
Performance characteristics of MAUI: an intelligent memory system architecture
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the “inte...
Justin Teller, Charles B. Silio Jr., Bruce L. Jaco...
SEKE
2005
Springer
16 years 21 days ago
Application of Design Combinatorial Theory to Scenario-Based Software Architecture Analysis
Design combinatorial theory for test-case generation has been used successfully in the past. It is useful in optimizing test cases as it is practically impossible to exhaustively t...
Chung-Horng Lung, Marzia Zaman