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ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
16 years 17 days ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
16 years 17 days ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek
ISCAS
2003
IEEE
93views Hardware» more  ISCAS 2003»
16 years 17 days ago
A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
Bing-Fei Wu, Chung-Fu Lin
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
16 years 16 days ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
ERLANG
2003
ACM
16 years 16 days ago
Extending the VoDKA architecture to improve resource modelling
VoDKA is a Video-on-Demand server developed using Erlang/OTP. In this paper, the evolution of the core architecture of the system, designed for improving resource modelling, is de...
Juan José Sánchez Penas, Carlos Abal...