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176
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DATE
2006
IEEE
153views Hardware» more  DATE 2006»
16 years 1 months ago
Analyzing timing uncertainty in mesh-based clock architectures
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
214
Voted
HICSS
2006
IEEE
141views Biometrics» more  HICSS 2006»
16 years 1 months ago
Infusing an Architectural Framework with Neo-Institutional Theory: Reports from Recent Change Management Initiatives within the
Swedish public administration is currently undergoing radical change towards dynamic models of governance relying on a high level of intergovernmental collaboration. This high lev...
Johan Magnusson, Andreas Nilsson
196
Voted
IPPS
2006
IEEE
16 years 1 months ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...
ISPASS
2006
IEEE
16 years 1 months ago
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures
The present work presents a cycle-level execution-driven simulator for modern GPU architectures. We discuss the simulation model used for our GPU simulator, based in the concept o...
Victor Moya Del Barrio, Carlos González, Jo...
AAAIDEA
2005
IEEE
16 years 1 months ago
Design and Evaluation of Diffserv Functionalities in the MPLS Edge Router Architecture
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
Wei-Chu Lai, Kuo-Ching Wu, Ting-Chao Hou