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ISCAS
2008
IEEE
144views Hardware» more  ISCAS 2008»
16 years 2 months ago
A novel VLSI iterative divider architecture for fast quotient generation
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
16 years 2 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
16 years 2 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
16 years 2 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
APSCC
2007
IEEE
16 years 1 months ago
Investigating the Potential of Service Oriented Architectures to Realize Dynamic Capabilities
The paradigm of service-oriented computing (SOC) has emerged as an architectural approach to flexibility and agility, not just in systems development but also in business process ...
Haresh Luthria, Fethi A. Rabhi, Michael Briers