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IEEEPACT
1999
IEEE
15 years 12 months ago
A Cost-Effective Clustered Architecture
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the fl...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
ISADS
1999
IEEE
15 years 12 months ago
CORBA based Architecture for Large Scale Workflow
Standard client-server workflow management systems have an intrinsic scalability limitation, the central server, which represents a bottleneck for large-scale applications. This s...
Roberto Silveira Silva Filho, Jacques Wainer, Edmu...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 12 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
MICRO
1999
IEEE
138views Hardware» more  MICRO 1999»
15 years 12 months ago
Dynamic 3D Graphics Workload Characterization and the Architectural Implications
Although PC-class 3D graphics hardware has made significant strides in the last several years, the underlying architectural design principles are still generally considered as a b...
Tulika Mitra, Tzi-cker Chiueh
FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
15 years 12 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose