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ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
16 years 4 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
ICCAD
2007
IEEE
125views Hardware» more  ICCAD 2007»
16 years 4 months ago
A methodology for timing model characterization for statistical static timing analysis
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Zhuo Feng, Peng Li
ICCAD
2005
IEEE
79views Hardware» more  ICCAD 2005»
16 years 4 months ago
Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators
— Standard small-signal analysis methods for circuits break down for oscillators because small input perturbations result in arbitrarily large output changes, thus invalidating f...
Ting Mei, Jaijeet S. Roychowdhury
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
16 years 4 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
ICCAD
2003
IEEE
154views Hardware» more  ICCAD 2003»
16 years 4 months ago
Length-Matching Routing for High-Speed Printed Circuit Boards
As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter. So, it becomes important to route the nets w...
Muhammet Mustafa Ozdal, Martin D. F. Wong