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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
CCGRID
2004
IEEE
15 years 10 months ago
Supporting quality of service in a non-dedicated opportunistic environment
In this paper we investigate the utilization of nondedicated, opportunistic resources in a desktop environment to provide statistical assurances to a class of QoS sensitive, soft ...
Jin Liang, Klara Nahrstedt
CCS
2006
ACM
15 years 10 months ago
TCG inside?: a note on TPM specification compliance
The Trusted Computing Group (TCG) has addressed a new generation of computing platforms employing both supplemental hardware and software with the primary goal to improve the secu...
Ahmad-Reza Sadeghi, Marcel Selhorst, Christian St&...
NGC
2000
Springer
15 years 10 months ago
The use of hop-limits to provide survivable ATM group communications
We examine the use of a hop-limit constraint with techniques to provide survivability for connection-oriented ATM group communications. A hop-limit constraint is an approach that ...
William Yurcik, David Tipper, Deep Medhi
INFOVIS
1995
IEEE
15 years 10 months ago
The information mural: a technique for displaying and navigating large information spaces
Visualizations which depict entire information spaces provide context for navigation and browsing tasks; however, the limited size of the display screen makes creating effective g...
Dean F. Jerding, John T. Stasko