1151 search results - page 192 / 231 » Automatic Generation of Complex Properties for Hardware Desi... |
223
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FCCM
2008
IEEE
16 years 1 months ago
2008
IEEE
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
166
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ISQED
2008
IEEE
16 years 1 months ago
2008
IEEE
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
181
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EUROMICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
—Current architectures for systems integration provide means for forming agile business processes by manually or dynamically configuring the components. However, a major challeng...
164
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FPL
2005
Springer
16 years 4 days ago
2005
Springer
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
143
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PVLDB
2010
15 years 5 months ago
2010
The huge amount of temporal data generated from many important applications call for a highly efficient and scalable version index. The TSB-tree has the potential of large scalab...