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ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
16 years 10 days ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...
176
Voted
ISQED
2005
IEEE
92views Hardware» more  ISQED 2005»
16 years 10 days ago
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourgu...
FPGA
2005
ACM
158views FPGA» more  FPGA 2005»
16 years 9 days ago
Automated synthesis for asynchronous FPGAs
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
Song Peng, David Fang, John Teifel, Rajit Manohar
IJCNLP
2004
Springer
16 years 4 days ago
A Study of Semi-discrete Matrix Decomposition for LSI in Automated Text Categorization
Abstract. This paper proposes the use of Latent Semantic Indexing (LSI) techniques, decomposed with semi-discrete matrix decomposition (SDD) method, for text categorization. The SD...
Qiang Wang, Xiaolong Wang, Guan Yi
176
Voted
COMPSAC
2003
IEEE
16 years 2 days ago
Automating Checking of Models Built Using a Graphically Based Formal Modelling Language
RDT is a graphical formal modelling language in which the modeller works by constructing diagrams of the processes in their model which they then join together to form complete sy...
Robert John Walters