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152
Voted
IPPS
1999
IEEE
15 years 11 months ago
1999
IEEE
Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequenc...
192
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WSTFEUS
2003
IEEE
16 years 8 days ago
2003
IEEE
— An error resilient architecture for video transmission over mobile wireless networks is presented. Radio link layer, transport layer, and application layer are combined to deal...
174
Voted
DAC
2003
ACM
16 years 7 days ago
2003
ACM
Coverage estimation for model checking quantifies the completeness of a set of properties. We present an improved version of the algorithm of Hoskote et al. [7] that applies to a...
181
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GLVLSI
2005
IEEE
16 years 18 days ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
185
Voted
IPPS
2002
IEEE
15 years 12 months ago
2002
IEEE
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ...