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IGPL
2010
97views more  IGPL 2010»
15 years 4 months ago
A symbolic/subsymbolic interface protocol for cognitive modeling
Researchers studying complex cognition have grown increasingly interested in mapping symbolic cognitive architectures onto subsymbolic brain models. Such a mapping seems essential...
Patrick Simen, Thad A. Polk
169
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ISICT
2003
15 years 7 months ago
A new approach for distributed computing in avionics systems
Historically, a typical avionics system architecture has been designed as a federated architecture of black-boxes with well-defined functions and implemented on fully dedicated co...
Miguel A. Sánchez-Puebla, Jesús Carr...
172
Voted
FPL
2007
Springer
146views Hardware» more  FPL 2007»
16 years 15 days ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
154
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HOTI
2005
IEEE
15 years 12 months ago
Performance Characterization of a 10-Gigabit Ethernet TOE
Though traditional Ethernet based network architectures such as Gigabit Ethernet have suffered from a huge performance difference as compared to other high performance networks (e...
Wu-chun Feng, Pavan Balaji, C. Baron, Laxmi N. Bhu...
ERSA
2006
98views Hardware» more  ERSA 2006»
15 years 7 months ago
Hydra: An Energy-efficient and Reconfigurable Network Interface
Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is us...
Marcel D. van de Burgwal, Gerard J. M. Smit, Gerar...