Sciweavers

3395 search results - page 178 / 679
» Circuit-aware architectural simulation
Sort
View
HPCA
2012
IEEE
14 years 2 months ago
BulkSMT: Designing SMT processors for atomic-block execution
Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior propo...
Xuehai Qian, Benjamin Sahelices, Josep Torrellas
EUROPAR
2004
Springer
16 years 14 days ago
Modular On-chip Multiprocessor for Routing Applications
Abstract. Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the caus...
Saifeddine Berrayana, Etienne Faure, Daniela Geniu...
196
Voted
MJ
2007
119views more  MJ 2007»
15 years 6 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
161
Voted
PADS
2003
ACM
16 years 10 days ago
Scalable RTI-Based Parallel Simulation of Networks
Federated simulation interfaces such as the High Level Architecture (HLA) were designed for interoperability, and as such are not traditionally associated with highperformance com...
Kalyan S. Perumalla, Alfred Park, Richard M. Fujim...
ICMCS
2005
IEEE
77views Multimedia» more  ICMCS 2005»
16 years 21 days ago
A quarter pel full search block motion estimation architecture for H.264/AVC
This paper presents a novel quarter pel full search block motion estimation architecture for H.264/AVC encoder. The proposed architecture is capable of calculating all 41 motion v...
Choudhury A. Rahman, Wael M. Badawy