169 search results - page 29 / 34 » Co-Scheduling Hardware and Software Pipelines |
214
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SBCCI
2009
ACM
16 years 1 months ago
2009
ACM
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
173
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ISHPC
2000
Springer
15 years 10 months ago
2000
Springer
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
176
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SIGCOMM
2000
ACM
15 years 10 months ago
2000
ACM
Routers must do a best matching pre x lookup for every packet solutions for Gigabit speeds are well known. As Internet link speeds higher, we seek a scalable solution whose speed ...
177
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IPPS
2007
IEEE
16 years 25 days ago
2007
IEEE
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
155
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ICDE
2010
IEEE
16 years 6 months ago
2010
IEEE
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...