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» Combining Model Reductions
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210
Voted
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
15 years 10 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
176
Voted
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
16 years 3 months ago
Combining cluster sampling with single pass methods for efficient sampling regimen design
Microarchitectural simulation is orders of magnitude slower than native execution. As more elements are accurately modeled, problems associated with slow simulation are further ex...
Paul D. Bryan, Thomas M. Conte
155
Voted
ICCAD
2002
IEEE
157views Hardware» more  ICCAD 2002»
16 years 3 months ago
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
Steven M. Martin, Krisztián Flautner, Trevo...
193
Voted
CVPR
2009
IEEE
17 years 1 months ago
Higher-Order Clique Reduction in Binary Graph Cut
We introduce a new technique that can reduce any higher-order Markov random field with binary labels into a first-order one that has the same minima as the original. Moreover, w...
Hiroshi Ishikawa 0002
184
Voted
DAC
2008
ACM
16 years 7 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta