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JSA
2000
116views more  JSA 2000»
15 years 7 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
JSA
2000
175views more  JSA 2000»
15 years 7 months ago
Complete worst-case execution time analysis of straight-line hard real-time programs
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...
Friedhelm Stappert, Peter Altenbernd
JSS
2000
85views more  JSS 2000»
15 years 7 months ago
An experimental comparison of reading techniques for defect detection in UML design documents
The basic motivation for software inspections is to detect and remove defects before they propagate to subsequent development phases where their detection and removal becomes more...
Oliver Laitenberger, Colin Atkinson, Maud Schlich,...
JUCS
2000
120views more  JUCS 2000»
15 years 7 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
15 years 7 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
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