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HIPEAC
2009
Springer
16 years 1 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
IPPS
2007
IEEE
16 years 1 months ago
On the Power of the Multiple Associative Computing (MASC) Model Related to That of Reconfigurable Bus-Based Models
: The MASC model is a multi-SIMD model that uses control parallelism to coordinate the interaction of data parallel threads. It supports a generalized associative style of parallel...
Mingxian Jin, Johnnie W. Baker
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
16 years 1 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
IPPS
2005
IEEE
16 years 23 days ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...