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178
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VLSID
2004
IEEE
16 years 7 months ago
2004
IEEE
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
202
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ISCA
2002
IEEE
16 years 3 days ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
191
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JETC
2008
15 years 5 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
216
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TWC
2010
15 years 1 months ago
2010
Abstract--In this paper we develop a new analytical methodology for the evaluation of the outage probability of cooperative decode-and-forward (DF) automatic-repeat-request (ARQ) r...
182
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DAC
2004
ACM
16 years 8 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...