82 search results - page 9 / 17 » Compiling code accelerators for FPGAs |
172
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TVLSI
2010
15 years 1 months ago
2010
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
163
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EURODAC
1995
IEEE
15 years 10 months ago
1995
IEEE
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
140
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FCCM
2007
IEEE
16 years 20 days ago
2007
IEEE
Abstract: FPGA-based acceleration of molecular dynamics (MD) has been the subject of several recent studies. Implementing long-range forces, however, has only recently been address...
176
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CHES
2009
Springer
16 years 6 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
182
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ERSA
2006
15 years 7 months ago
2006
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...