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» Completeness of Neighbourhood Logic
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DATE
2008
IEEE
121views Hardware» more  DATE 2008»
16 years 1 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
172
Voted
ATVA
2007
Springer
108views Hardware» more  ATVA 2007»
16 years 1 months ago
A New Approach to Bounded Model Checking for Branching Time Logics
Abstract. Bounded model checking (BMC) is a technique for overcoming the state explosion problem which has gained wide industrial acceptance. Bounded model checking is typically ap...
Rotem Oshman, Orna Grumberg
197
Voted
JELIA
2004
Springer
16 years 12 days ago
Towards a Logical Analysis of Biochemical Pathways
Biochemical pathways or networks are generic representations used to model many different types of complex functional and physical interactions in biological systems. Models based ...
Patrick Doherty, Steve Kertes, Martin Magnusson, A...
211
Voted
CSFW
2003
IEEE
16 years 10 days ago
Understanding SPKI/SDSI Using First-Order Logic
SPKI/SDSI is a language for expressing distributed access control policy, derived from SPKI and SDSI. We provide a first-order logic (FOL) semantics for SDSI, and show that it ha...
Ninghui Li, John C. Mitchell
DAC
2003
ACM
16 years 8 days ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...