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IPPS
2005
IEEE
16 years 19 days ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
194
Voted
MOBICOM
2009
ACM
16 years 1 months ago
A scalable micro wireless interconnect structure for CMPs
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, So...
207
Voted
VR
2002
IEEE
125views Virtual Reality» more  VR 2002»
15 years 12 months ago
A Scalable, Multi-User VRML Server
VRML97 allows the description of dynamic worlds that can change with both the passage of time, and user interaction. Unfortunately, the current VRML usage model prevents its full ...
Thomas Rischbeck, Paul Watson
202
Voted
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 11 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
239
Voted
RTAS
1997
IEEE
15 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford