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» Criteria for the evaluation of implemented architectures
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PLDI
1994
ACM
15 years 11 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
211
Voted
DAC
2008
ACM
15 years 8 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
207
Voted
ISPDC
2010
IEEE
15 years 5 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
292
Voted
VLDB
2005
ACM
146views Database» more  VLDB 2005»
16 years 7 months ago
Adaptive website recommendations with AWESOME
Recommendations are crucial for the success of large websites. While there are many ways to determine recommendations, the relative quality of these recommenders depends on many fa...
Andreas Thor, Nick Golovin, Erhard Rahm
ICAC
2008
IEEE
16 years 1 months ago
An Adaptive Middleware for Supporting Time-Critical Event Response
Abstract— There are many applications where a timely response to an important event is needed. Often such response can require significant computation and possibly communication...
Qian Zhu, Gagan Agrawal