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SLIP
2009
ACM
16 years 1 months ago
Closed-form solution for timing analysis of process variations on SWCNT interconnect
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
Peng Sun, Rong Luo
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
16 years 1 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
DAC
2000
ACM
16 years 8 months ago
On switch factor based analysis of coupled RC interconnects
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
DSOM
2000
Springer
15 years 11 months ago
Operational Data Analysis: Improved Predictions Using Multi-computer Pattern Detection
Operational Data Analysis (ODA) automatically 1) monitors the performance of a computer through time, 2) stores such information in a data repository, 3) applies data-mining techn...
Ricardo Vilalta, Chidanand Apté, Sholom M. ...
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
16 years 4 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...