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ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
16 years 1 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
CCGRID
2009
IEEE
16 years 1 months ago
Performance under Failures of DAG-based Parallel Computing
— As the scale and complexity of parallel systems continue to grow, failures become more and more an inevitable fact for solving large-scale applications. In this research, we pr...
Hui Jin, Xian-He Sun, Ziming Zheng, Zhiling Lan, B...
INFOCOM
2009
IEEE
16 years 1 months ago
Interference-Aware MAC Protocol for Wireless Networks by a Game-Theoretic Approach
—We propose an interference-aware MAC protocol using a simple transmission strategy motivated by a gametheoretic approach. We formulate a channel access game, which considers nod...
HyungJune Lee, Hyukjoon Kwon, Arik Motskin, Leonid...
WWIC
2009
Springer
109views Communications» more  WWIC 2009»
16 years 1 months ago
On Prolonging Sensornode Gateway Lifetime by Adapting Its Duty Cycle
In this paper we discuss the lifetime of an battery powered device which acts as a gateway between a wireless sensor network and a standard network. The wireless communication stan...
Marcin Brzozowski, Peter Langendoerfer
EUROPAR
2009
Springer
16 years 1 months ago
A Multilevel Parallelization Framework for High-Order Stencil Computations
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard ...