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ICPP
2006
IEEE
16 years 1 months ago
Address-Value Decoupling for Early Register Deallocation
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...
ICRA
2006
IEEE
131views Robotics» more  ICRA 2006»
16 years 1 months ago
Using Reinforcement Learning to Improve Exploration Trajectories for Error Minimization
Abstract— The mapping and localization problems have received considerable attention in robotics recently. The exploration problem that drives mapping has started to generate sim...
Thomas Kollar, Nicholas Roy
INFOCOM
2006
IEEE
16 years 1 months ago
On Hybrid Collision Control for IEEE 802.11 Ad-Hoc Networks
— We present in this work a new mechanism based on an innovative hybrid approach for traffic and collision control in wireless ad hoc networks. We combine the well known equatio...
Hicham Khalife
IOLTS
2006
IEEE
103views Hardware» more  IOLTS 2006»
16 years 1 months ago
Designing Robust Checkers in the Presence of Massive Timing Errors
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
Frederic Worm, Patrick Thiran, Paolo Ienne
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
16 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...