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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
16 years 9 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
VLDB
2001
ACM
109views Database» more  VLDB 2001»
15 years 11 months ago
Analyzing energy behavior of spatial access methods for memory-resident data
The proliferation of mobile and pervasive computing devices has brought energy constraints into the limelight, together with performance considerations. Energy-conscious design is...
Ning An, Anand Sivasubramaniam, Narayanan Vijaykri...
PG
2000
IEEE
15 years 11 months ago
Dynamic PDE Surfaces with Flexible and General Geometric Constraints
PDE surfaces, whose behavior is governed by Partial Differential Equations (PDEs), have demonstrated many modeling advantages in surface blending, free-form surface modeling, and ...
Haixia Du, Hong Qin
MOBICOM
2000
ACM
15 years 11 months ago
An end-to-end approach to host mobility
We present the design and implementation of an end-to-end architecture for Internet host mobility using dynamic updates to the Domain Name System (DNS) to track host location. Exi...
Alex C. Snoeren, Hari Balakrishnan
DEXA
2000
Springer
132views Database» more  DEXA 2000»
15 years 11 months ago
Improving the Performance of High-Energy Physics Analysis through Bitmap Indices
Abstract. Bitmap indices are popular multi-dimensional data structures for accessing read-mostly data such as data warehouse (DW) applications, decision support systems (DSS) and o...
Kurt Stockinger, Dirk Düllmann, Wolfgang Hosc...
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