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» Design considerations for MRAM
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CASES
2008
ACM
15 years 9 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
209
Voted
CIKM
2008
Springer
15 years 9 months ago
Classifying networked entities with modularity kernels
Statistical machine learning techniques for data classification usually assume that all entities are i.i.d. (independent and identically distributed). However, real-world entities...
Dell Zhang, Robert Mao
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
15 years 9 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
DAC
2005
ACM
15 years 9 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
189
Voted
ISLPED
2007
ACM
99views Hardware» more  ISLPED 2007»
15 years 8 months ago
Thermal-aware task scheduling at the system software level
Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an ad...
Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, H...