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SLIP
2006
ACM
16 years 1 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
IWQOS
2004
Springer
16 years 19 days ago
Topology design for service overlay networks with bandwidth guarantees
— The Internet still lacks adequate support for QoS applications with real-time requirements. In great part, this is due to the fact that provisioning of end-to-end QoS to traf...
S. L. Vieira, Jörg Liebeherr
ISQED
2003
IEEE
92views Hardware» more  ISQED 2003»
16 years 17 days ago
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...
Makram M. Mansour, Mohammad M. Mansour, Amit Mehro...
CASES
2000
ACM
15 years 11 months ago
A code generation framework for Java component-based designs
In this paper, we describe a software architecture supporting code generation from within Ptolemy II. Ptolemy II is a componentbased design tool intended for embedded and real-tim...
Jeff Tsay, Christopher Hylands, Edward Lee
COLT
2000
Springer
15 years 11 months ago
On the Learnability and Design of Output Codes for Multiclass Problems
Output coding is a general framework for solving multiclass categorization problems. Previous research on output codes has focused on building multiclass machines given predefine...
Koby Crammer, Yoram Singer