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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
16 years 1 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ESCIENCE
2006
IEEE
16 years 1 months ago
TextGrid and eHumanities
TextGrid is a new Grid project in the framework of the German D-Grid initiative, with the aim to deploy Grid technologies for humanities scholars working on historical (German) te...
Peter Gietz, Andreas Aschenbrenner, Stefan Bü...
GLOBECOM
2006
IEEE
16 years 1 months ago
High-rate, Double-Symbol-Decodable STBCs from Clifford Algebras
— For the number of transmit antennas N = 2a the maximum rate (in complex symbols per channel use) of all the Quasi-Orthogonal Designs (QODs) reported in the literature is a 2aâˆ...
Sanjay Karmakar, B. Sundar Rajan
GLOBECOM
2006
IEEE
16 years 1 months ago
Non-linear Turbo Codes for Interleaver-Division Multiple Access on the OR Channel
Abstract— This paper presents an Interleaver-Division Multiple Access (IDMA) based architecture with single-user decoding using parallel concatenated non-linear trellis codes (PC...
Miguel Griot, Andres I. Vila Casado, Richard D. We...
GLOBECOM
2006
IEEE
16 years 1 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
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