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GLVLSI
2011
IEEE
351views VLSI» more  GLVLSI 2011»
14 years 11 months ago
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos&...
199
Voted
ICIP
2003
IEEE
16 years 9 months ago
Design of Q-shift complex wavelets for image processing using frequency domain energy minimization
This paper proposes a new method of designing finitesupport wavelet filters, based on minimization of energy in key parts of the frequency domain. In particular this technique is ...
Nick G. Kingsbury
145
Voted
DAC
2005
ACM
16 years 8 months ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid ...
167
Voted
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
16 years 1 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
191
Voted
SLIP
2006
ACM
16 years 1 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...