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VLSID
2005
IEEE
127views VLSI» more  VLSID 2005»
16 years 23 days ago
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pa...
CAISE
2005
Springer
16 years 22 days ago
A language for modeling enterprise contextual ontologies
To achieve inter-enterprise software interoperability, the semantics of interchanged information by using electronic business documents, has to be explicitly modeled. A common appr...
María Laura Caliusco, César Maidana,...
ASSETS
2004
ACM
16 years 19 days ago
The audio abacus: representing numerical values with nonspeech sound for the visually impaired
Point estimation is a relatively unexplored facet of sonification. We present a new computer application, the Audio Abacus, designed to transform numbers into tones following the ...
Bruce N. Walker, Jeff Lindsay, Justin Godfrey
ICS
2004
Tsinghua U.
16 years 17 days ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
16 years 14 days ago
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H...