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ICCD
2008
IEEE
148views Hardware» more  ICCD 2008»
16 years 2 months ago
Adaptive SRAM memory for low power and high yield
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jaco...
ISCA
2008
IEEE
137views Hardware» more  ISCA 2008»
16 years 1 months ago
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
Engin Ipek, Onur Mutlu, José F. Martí...
ISCAS
2007
IEEE
129views Hardware» more  ISCAS 2007»
16 years 1 months ago
ECC Processor with Low Die Size for RFID Applications
Abstract— This paper presents the design of a special purpose processor with Elliptic Curve Digital Signature Algorithm (ECDSA) functionality. This digital signature generation d...
Franz Fürbass, Johannes Wolkerstorfer
MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
16 years 1 months ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
RTCSA
2007
IEEE
16 years 1 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...