4394 search results - page 628 / 879 » Designing agent chips |
180
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DATE
2005
IEEE
16 years 27 days ago
2005
IEEE
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
228
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DFT
2005
IEEE
16 years 27 days ago
2005
IEEE
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
166
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GLVLSI
2005
IEEE
16 years 27 days ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
184
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IEEEPACT
2005
IEEE
16 years 26 days ago
2005
IEEE
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
223
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INFOCOM
2005
IEEE
16 years 26 days ago
2005
IEEE
Packet Classification (PC) has been a critical data path function for many emerging networking applications. An interesting approach is the use of TCAM to achieve deterministic, hi...