4394 search results - page 94 / 879 » Designing agent chips |
169
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ICCAD
1995
IEEE
15 years 10 months ago
1995
IEEE
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
161
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IAT
2007
IEEE
16 years 1 months ago
2007
IEEE
Optimal design is intractable in general. We identify a tractable class of design problems and propose the first framework for efficient, decision-theoretically optimal, collabo...
159
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...
134
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
156
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...