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EURODAC
1994
IEEE
94views VHDL» more  EURODAC 1994»
15 years 11 months ago
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
Richard McGowen, F. Joel Ferguson
DELTA
2006
IEEE
15 years 11 months ago
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
Jia Di, Dilip P. Vasudevan
FM
2006
Springer
148views Formal Methods» more  FM 2006»
15 years 11 months ago
Automatic Translation from Circus to Java
Abstract. Circus is a combination of Z and CSP that supports the development of state-rich reactive systems based on refinement. In this paper we present JCircus, a tool that autom...
Angela Freitas, Ana Cavalcanti
FPL
2006
Springer
223views Hardware» more  FPL 2006»
15 years 11 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
FOSSACS
2008
Springer
15 years 9 months ago
Robust Analysis of Timed Automata via Channel Machines
Whereas formal verification of timed systems has become a very active field of research, the idealised mathematical semantics of timed automata cannot be faithfully implemented. Se...
Patricia Bouyer, Nicolas Markey, Pierre-Alain Reyn...