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DATE
2009
IEEE
79views Hardware» more  DATE 2009»
16 years 1 months ago
Solver technology for system-level to RTL equivalence checking
—Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, ...
Alfred Kölbl, Reily Jacoby, Himanshu Jain, Ca...
DSD
2008
IEEE
95views Hardware» more  DSD 2008»
16 years 1 months ago
Programmable Numerical Function Generators for Two-Variable Functions
This paper proposes a design method and programmable architectures for numerical function generators (NFGs) of two-variable functions. To realize a two-variable function in hardwa...
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
ACSD
2006
IEEE
129views Hardware» more  ACSD 2006»
16 years 1 months ago
Communicating with Synchronized Environments
In the modern design environments, different modules, available in existent libraries, may obey different architectural styles and execution models. Reaching a well– behaved com...
Tiberiu Seceleanu, Axel Jantsch
ICCS
2004
Springer
16 years 16 days ago
Evolutionary State Assignment for Synchronous Finite State Machines
: Synchronous finite state machines are very important for digital sequential designs. Among other important aspects, they represent a powerful way for synchronizing hardware comp...
Nadia Nedjah, Luiza de Macedo Mourelle
FPL
2009
Springer
90views Hardware» more  FPL 2009»
15 years 11 months ago
A toolset for the analysis and optimization of motion estimation algorithms and processors
This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and ...
Trevor Spiteri, George Vafiadis, Jose Luis Nunez-Y...