Sciweavers

3236 search results - page 235 / 648
» Designing better phages
Sort
View
FPL
2004
Springer
90views Hardware» more  FPL 2004»
16 years 19 days ago
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...
IEEEPACT
2003
IEEE
16 years 16 days ago
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
In Thread-Level Speculation (TLS), speculative tasks generate memory state that cannot simply be combined with the rest of the system because it is unsafe. One way to deal with th...
María Jesús Garzarán, Milos P...
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
16 years 15 days ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
HRI
2009
ACM
15 years 12 months ago
Nonverbal leakage in robots: communication of intentions through seemingly unintentional behavior
Human communication involves a number of nonverbal cues that are seemingly unintentional, unconscious, and automatic—both in their production and perception—and convey rich in...
Bilge Mutlu, Fumitaka Yamaoka, Takayuki Kanda, Hir...
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
15 years 11 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...