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IPPS
2006
IEEE
16 years 1 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
16 years 1 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
16 years 1 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
RTSS
2006
IEEE
16 years 1 months ago
Mutual Consistency in Real-Time Databases
A real-time database is composed of real-time objects whose values remain valid only within their validity intervals. Each object in the database models a real world entity. The f...
Abhay Kumar Jha, Ming Xiong, Krithi Ramamritham
RTSS
2006
IEEE
16 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
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