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FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
16 years 1 days ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
16 years 4 hour ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ASPLOS
2000
ACM
15 years 12 months ago
Thread Level Parallelism and Interactive Performance of Desktop Applications
Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear f...
Krisztián Flautner, Richard Uhlig, Steven K...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 12 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
PADS
1999
ACM
15 years 12 months ago
Shock Resistant Time Warp
In an attempt to cope with time-varying workload, traditional adaptive Time Warp protocols are designed to react in response to performance changes by altering control parameter c...
Alois Ferscha, James Johnson
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