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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
CASES
2006
ACM
16 years 1 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
229
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MM
2006
ACM
125views Multimedia» more  MM 2006»
16 years 1 months ago
The design of a real-time, multimodal biofeedback system for stroke patient rehabilitation
This paper presents a novel real-time, multi-modal biofeedback system for stroke patient therapy. The problem is important as traditional mechanisms of rehabilitation are monotono...
Yinpeng Chen, He Huang, Weiwei Xu, Richard Isaac W...
INFOCOM
2005
IEEE
16 years 1 months ago
A performance vs. cost framework for evaluating DHT design tradeoffs under churn
Abstract— Protocols for distributed hash tables (DHTs) incorporate features to achieve low latency for lookup requests in the face of churn, continuous changes in membership. The...
Jinyang Li, Jeremy Stribling, Robert Morris, M. Fr...
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
16 years 1 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong