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ISHPC
2003
Springer
16 years 11 days ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
CHI
2010
ACM
16 years 9 days ago
Clutching at straws: using tangible interaction to provide non-visual access to graphs
We present a tangible user interface (TUI) called Tangible Graph Builder, that has been designed to allow visually impaired users to access graph and chart-based data. We describe...
David K. McGookin, Euan Robertson, Stephen A. Brew...
DATE
2010
IEEE
162views Hardware» more  DATE 2010»
16 years 8 days ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...
ICPPW
2002
IEEE
16 years 3 days ago
A Structural Framework for Modeling Multi-Stage Network Attacks
Incidents such as Solar Sunrise and Nimda demonstrate the need to expressively model distributed and complex network attacks. To protect information systems, system administrators...
Kristopher Daley, Ryan Larson, Jerald Dawkins
WSE
2002
IEEE
16 years 2 days ago
Dynamic Model Extraction and Statistical Analysis of Web Applications
The World Wide Web, initially intended as a way to publish static hypertexts on the Internet, is moving toward complex applications. Static Web sites are being gradually replaced ...
Paolo Tonella, Filippo Ricca
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