96 search results - page 6 / 20 » Device and architecture co-optimization for FPGA power reduc... |
168
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FTEDA
2007
15 years 6 months ago
2007
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their archite...
194
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ICIP
2006
IEEE
16 years 8 months ago
2006
IEEE
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
163
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TVLSI
2008
15 years 6 months ago
2008
A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
190
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FCCM
2006
IEEE
16 years 20 days ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
149
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...