The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
—On-die capacitances interact with the inductance and resistance of the power distribution network to supply electrical charge. A distributed model is generally required to analy...
Michael Sotman, Avinoam Kolodny, Mikhail Popovich,...
Abstract--In this paper, we present an unequal power allocation technique to increase the throughput of code-division multiple-access (CDMA) systems with chip-level interleavers. P...
The web graph follows the power law distribution and has a hierarchy structure. But neither the PageRank algorithm nor any of its improvements leverage these attributes. In this p...
Yizhou Lu, Benyu Zhang, Wensi Xi, Zheng Chen, Yi L...