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DSD
2006
IEEE
107views Hardware» more  DSD 2006»
16 years 1 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
188
Voted
APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
15 years 10 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
16 years 7 months ago
16-Bit Segmented Type Current Steering DAC for Video Applications
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
Gaurav Raja, Basabi Bhaumik
AAAI
1996
15 years 8 months ago
Trajectory Constraints in Qualitative Simulation
We present a method for specifying temporal constraints on trajectories of dynamical systems and enforcing them during qualitative simulation. This capability can be used to focus...
Giorgio Brajnik, Daniel J. Clancy
JUCS
2008
147views more  JUCS 2008»
15 years 7 months ago
Cost Model for Bitstream Access Services with QoS Parameters
: The European Regulator Group (ERG) defines Bitstream Access Service as a wholesale service offered by a broadband network operator with significant market power to an Internet Se...
Laura Rodríguez de Lope, Klaus D. Hackbarth