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180
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HOTI
2005
IEEE
16 years 1 months ago
2005
IEEE
Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bo...
212
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HOTI
2005
IEEE
16 years 1 months ago
2005
IEEE
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...
230
Voted
HPCA
2005
IEEE
16 years 1 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
199
Voted
HPCA
2005
IEEE
16 years 1 months ago
2005
IEEE
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
194
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ICCAD
2005
IEEE
16 years 1 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...