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203
Voted
EUROPAR
2005
Springer
16 years 17 days ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
168
Voted
ICPP
2003
IEEE
16 years 10 days ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
203
Voted
IPPS
2002
IEEE
15 years 12 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
163
Voted
CCGRID
2004
IEEE
15 years 10 months ago
2004
IEEE
1 Scheduling resources on Grids is a well-known problem. The extension of Grids to LambdaGrids requires scheduling of lambdas, i.e., end-to-end high-speed circuits. In this paper, ...
204
Voted
GRID
2008
Springer
15 years 8 months ago
2008
Springer
Desktop Grids have emerged as an important methodology to harness the idle cycles of millions of participant desktop PCs over the Internet. However, to effectively utilize the res...