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HPCC
2009
Springer
15 years 12 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
HPCA
1998
IEEE
15 years 11 months ago
The Sensitivity of Communication Mechanisms to Bandwidth and Latency
The goal of this paper is to gain insight into the relative performance of communication mechanisms as bisection bandwidth and network latency vary. We compare shared memory with ...
Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren,...
IPPS
1996
IEEE
15 years 11 months ago
Kiloprocessor Extensions to SCI
To expand the Scalable Coherent Interface's (SCI) capabilities so it can be used to efficiently handle sharing in systems of hundreds or even thousands of processors, the SCI...
Stefanos Kaxiras
EUROPAR
2010
Springer
15 years 8 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
NCA
2009
IEEE
16 years 2 months ago
Seed Scheduling for Peer-to-Peer Networks
—The initial phase in a content distribution (file sharing) scenario is delicate due to the lack of global knowledge and the dynamics of the overlay. An unwise distribution of t...
Flavio Esposito, Ibrahim Matta, Pietro Michiardi, ...