This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...
Given the decreasing cost of non-volatile RAM (NVRAM), by the late 1990's it will be feasible for most workstations to include a megabyte or more of NVRAM, enabling the desig...
Mary Baker, Satoshi Asami, Etienne Deprit, John K....
Basic approaches to computer lab management range along a spectrum from total lockdown of lab computers to total freedom. Total lockdown, which can be implemented with system perm...
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...