Sciweavers

2620 search results - page 165 / 524
» Efficient Hardware Voxelization
Sort
View
DAC
2002
ACM
16 years 8 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti...
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
16 years 7 months ago
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, H...
HPCA
2003
IEEE
16 years 7 months ago
Caches and Hash Trees for Efficient Memory Integrity
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, M...
SIPS
2007
IEEE
16 years 1 months ago
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations
A hardware ef cient approach is introduced for elementary function evaluations in certain structured matrix computations. It is a comprehensive approach that utilizes lookup table...
Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabar...
ICMCS
2005
IEEE
109views Multimedia» more  ICMCS 2005»
16 years 18 days ago
An Efficient Architecture for Lifting-Based Forward and Inverse Discrete Wavelet Transform
In this research, an architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed. The proposed architecture reduces the hardware requi...
S. Mayilavelane Aroutchelvame, Kaamran Raahemifar