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DAC
2003
ACM
15 years 12 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
16 years 18 days ago
DSP engine design for LINC wireless transmitter systems
—Linear amplification with nonlinear components (LINC) technique is a linearization technique for power amplifier designs. By using LINC, the nonlinear power amplifier with high ...
Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai...
ASPDAC
1998
ACM
72views Hardware» more  ASPDAC 1998»
15 years 10 months ago
Space- and Time-Efficient BDD Construction via Working Set Control
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
Bwolen Yang, Yirng-An Chen, Randal E. Bryant, Davi...
VLSID
1993
IEEE
133views VLSI» more  VLSID 1993»
15 years 10 months ago
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
V. Visvanathan, Nibedita Mohanty, S. Ramanathan
GLOBECOM
2007
IEEE
15 years 8 months ago
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, And...