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FPL
2006
Springer
242views Hardware» more  FPL 2006»
15 years 10 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
HIPC
2000
Springer
15 years 10 months ago
Improving Offset Assignment on Embedded Processors Using Transformations
Embedded systems consisting of the application program ROM, RAM, the embedded processor core and any custom hardware on a single wafer are becoming increasingly common in areas suc...
Sunil Atri, J. Ramanujam, Mahmut T. Kandemir
FUN
2010
Springer
230views Algorithms» more  FUN 2010»
15 years 10 months ago
O(1)-Time Unsorting by Prefix-Reversals in a Boustrophedon Linked List
Conventional wisdom suggests that O(k)-time is required to reverse a substring of length k. To reduce this time complexity, a simple and unorthodox data structure is introduced. A ...
Aaron Williams
GLVLSI
2010
IEEE
149views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Lightweight runtime control flow analysis for adaptive loop caching
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
Marisha Rawlins, Ann Gordon-Ross
CODES
2007
IEEE
15 years 8 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu